參數(shù)資料
型號(hào): STPCI2GDY
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù): 46/111頁(yè)
文件大?。?/td> 1896K
代理商: STPCI2GDY
ELECTRICAL SPECIFICATIONS
46/111
Issue 1.0 - July 24, 2002
4.5. AC CHARACTERISTICS
This section lists the AC characteristics of the
STPC interfaces including output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1
and
Figure 4-2
. The rising clock edge
reference level VREF and other reference levels
are shown in
Table 4-9
below. Input or output
signals must cross these levels during testing.
Figure 4-1
shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
Note: Refer to
Figure 4-1
.
Table 4-9. Drive Level and Measurement Points for Switching Characteristics
Symbol
V
REF
V
IHD
V
ILD
Value
1.5
2.5
0.0
Units
V
V
V
Figure 4-1. Drive Level and Measurement Points for Switching Characteristics
CLK:
V
Ref
V
ILD
V
IHD
Tx
LEGEND:
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
V
Ref
Valid
Input
Valid
Output n+1
Valid
Output n
OUTPUTS:
INPUTS:
MAX
MIN
A
B
C
D
V
Ref
V
ILD
V
IHD
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