參數(shù)資料
型號(hào)： STPCD0110BTC3
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 44/61頁(yè)
文件大?。?/td> 1007K
代理商： STPCD0110BTC3
ELECTRICAL SPECIFICATIONS
44/61
Issue 2.2 - October 13, 2000
24
4
IOR#, IOW# asserted before SA[19:0]
24o
4
I/O access to 16 bit ISA Slave Standard cycle
24r
4
I/O access to 16 bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before next ALE# asserted
25b
4
Memory access to 16 bit ISA Slave Standard cycle
25d
4
Memory access to 8 bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before next ALE# aserted
25e
4
Memory access to 16 bit ISA Slave - 2BCLK
25f
4
Memory access to 16 bit ISA Slave Standard cycle
25h
4
Memory access to 8 bit ISA Slave Standard cycle
IOR#, IOW# asserted before next ALE# asserted
25i
4
I/O access to 16 bit ISA Slave Standard cycle
25k
4
I/O access to 16 bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
26b
4
Memory access to 16 bit ISA Slave Standard cycle
26d
4
Memory access to 8 bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f
4
Memory access to 16 bit ISA Slave Standard cycle
26h
4
Memory access to 8 bit ISA Slave Standard cycle
IOR#, IOW# asserted before next IOR#, IOW# asserted
26i
4
I/O access to 16 bit ISA Slave Standard cycle
26k
4
I/O access to 8 bit ISA Slave Standard cycle
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
28a
4
Memory access to 16 bit ISA Slave
28b
4
Memory access to 8 bit ISA Slave
Any command negated to IOR#, IOW# asserted
28c
4
I/O access to ISA Slave
MEMR#, MEMW# negated before next ALE# asserted
SMEMR#, SMEMW# negated before next ALE# asserted
IOR#, IOW# negated before next ALE# asserted
LA[23:17] valid to IOCHRDY negated
33a
4
Memory access to 16 bit ISA Slave - 4 BCLK
33b
4
Memory access to 8 bit ISA Slave - 7 BCLK
LA[23:17] valid to read data valid
34b
4
Memory access to 16 bit ISA Slave Standard cycle
34e
4
Memory access to 8 bit ISA Slave Standard cycle
ALE# asserted to IOCHRDY# negated
37a
4
Memory access to 16 bit ISA Slave - 4 BCLK
37b
4
Memory access to 8 bit ISA Slave - 7 BCLK
37c
4
I/O access to 16 bit ISA Slave - 4 BCLK
37d
4
I/O access to 8 bit ISA Slave - 7 BCLK
ALE# asserted to read data valid
38b
4
Memory access to 16 bit ISA Slave Standard Cycle
38e
4
Memory access to 8 bit ISA Slave Standard Cycle
38h
4
I/O access to 16 bit ISA Slave Standard Cycle
Note; The signal numbering refers to
Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
19T
19T
Cycles
Cycles
25
4
10T
10T
Cycles
Cycles
25
4
10T
10T
10T
Cycles
Cycles
Cycles
25
4
10T
10T
Cycles
Cycles
26
4
12T
12T
Cycles
Cycles
26
4
12T
12T
Cycles
Cycles
26
4
12T
12T
Cycles
Cycles
28
4
3T
3T
Cycles
Cycles
28
4
3T
1T
1T
1T
Cycles
Cycles
Cycles
Cycles
29a
4
29b
4
29c
4
33
4
8T
14T
Cycles
Cycles
34
4
8T
14T
Cycles
Cycles
37
4
6T
12T
6T
12T
Cycles
Cycles
Cycles
Cycles
38
4
4T
10T
4T
Cycles
Cycles
Cycles
Table 4-8. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
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