參數(shù)資料
型號(hào)： STPCD0110BTC3
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 42/61頁(yè)
文件大?。?/td> 1007K
代理商： STPCD0110BTC3
ELECTRICAL SPECIFICATIONS
42/61
Issue 2.2 - October 13, 2000
4.5.7 ISA INTERFACE AC TIMING CHARCTERISTICS
Figure 4-10 ISA Cycle (ref table
Table 4-8
)
Note 1; Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
Note; The clock has not been represented as it cannot be accuratly represented depending on the ISA Slave mode.
Valid AENx
Valid Address
Valid Address, SBHE*
V.Dat
VALID DATA
54
28
26
64
59
58
55
23
61
48
47
57
27
24
42
41
10
11
34
33
3
22
56
29
25
9
18
2
12
38
37
15
14
13
ALE
AEN
LA [23:17]
SA [19:0]
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
Table 4-8. ISA Bus AC Timing
Name
2
4
3
4
Parameter
LA[23:17] valid before ALE# negated
LA[23:17] valid before MEMR#, MEMW# asserted
3a
4
Memory access to 16 bit ISA Slave
3b
4
Memory access to 8 bit ISA Slave
SA[19:0] & SBHE valid before ALE# negated
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a
4
Memory access to 16 bit ISA Slave
10b
4
Memory access to 8 bit ISA Slave
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c
4
Memory access to 16 bit ISA Slave
10d
4
Memory access to 8 bit ISA Slave
Note; The signal numbering refers to
Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
Min
5T
Max
Units
Cycles
5T
5T
1T
Cycles
Cycles
Cycles
9
4
10
4
2T
2T
Cycles
Cycles
10
4
2T
2T
Cycle
Cycle
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