參數(shù)資料
型號(hào)： STPCD0110BTC3
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 40/61頁(yè)
文件大?。?/td> 1007K
代理商： STPCD0110BTC3
ELECTRICAL SPECIFICATIONS
40/61
Issue 2.2 - October 13, 2000
Table 4-5. AC Memory Timing Characteristics
Parameter
HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3)
HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3)
HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3)
HCLK (or GCLK2X) to MWE# valid (see Note 3)
HCLK to MD[63:0] bus valid (see Note 3)
GCLK2X to MD[63:0] bus valid (see Note 3)
MD[63:0] Generic hold
Column Address Hold Time
CAS Hold Time
Data Hold TIme from CAS Low
CAS Precharge Time
CAS to RAS Precharge Time
CAS Low to RAS HIGH (Write only)
CAS Setup Time
Data In Setup Time
Row Address Hold Time
RAS Pulse Width
Random Read or Write Time Cycle
RAS to CAS Delay Time
Read Command Hold Time
Read Command Setup Time
RAS Precharge Time
Write Command Hold Time
WE Command Setup Time
WE Hold Time
WE Setup Time
Column Address Hold Time from RAS
RAS to valid Column Address Delay
Column Address to RAS Setup Time
Write Command Hold Reference to RAS
Write Command to RAS Setup Time (Note 2)
Write Command to CAS Setup Time (Note 2)
Data Hold Reference to RAS
RAS High to CAS Low Precharge
CAS Before RAS Setup Time
CAS Before RAS Hold Time
CAS Hold Time after RAS
Note 1; T
Cycle
x n
CAS
+ (t
Data off
- t
CAS out
)
Where T
Cycle
is the the number of clock cycles.
n
CAS
is the number of CAS Cycles (see
section 6.7.
)
T
Dataoff
is the Generic Datahold
t
CAS Out
the CLK (either HCLK or GCLK2X) to CAS Low.
T
Dataoff
and t
CAS Out
are used to refine the timing programming.
Note 2; Value to be derived from CAS pulse width which is programmable (see
section 6.7.
).
Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X
Note 4; These timings are extracted from simulations and are not garanteed by testing
Min
Max
17
17
17
17
25
23
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCRAS
tCCAS
tCMA
tCMWE
tCMD
tGCMD
tMDG
tCAH
4
tCHR
4
tCOH
4
tCPN
4
tCRP
4
tCRW
4
tCSR
4
tDS
4
tRAH
4
tRAS
4
tRC
4
tRCD
4
tRCH
4
tRCS
4
tRP
4
tWCH
4
tWCS
4
tWRH
4
tWRP
4
tAR
4
tRAD
4
tRAL
4
tWCR
4
tRWL
4
tCWL
4
tDHR
4
tRPC
4
tCRS
4
tCHR
4
tCSH
4
0
≥
1T
Cycles
≥
1T
Cycles
Note 1
1T
Cycles
≤
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
3T
Cycles
≥
6T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
2T
Cycles
≥
1T
Cycles
≥
1T
Cycles
Note 2
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
2T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
3T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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