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參數資料
| 型號： | STP2223BGA |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數： | 32/34頁 |
| 文件大小： | 476K |
| 代理商： | STP2223BGA |
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7
UPA to PCI Interface
U2P
STP2223BGA
July 1997
Interrupt block
Mondo Dispatch Unit (MDU):
In the Sun-4U architecture, interrupts to a processor are sent as packets on the
UPA bus. The MDU in U2P is a system resource for generating such packets. The MDU accepts interrupt
requests from the UPA slave ports, PCI busses and internal U2P sources and dispatches interrupt packets to
the UPA.
Internal Control
Merge Buffer: In order to allow sub-line writes into a 64-byte memory line, it is necessary to perform a
read-modify-write operation on the UPA. The Merge Buffer is responsible for generating the correct UPA
read, merging the partial line, and writing the whole block to the UPA.
PIO Control: Decodes slave requests from the UPA_A request FIFO, arbitrates for the appropriate resource
and dispatches the request.
Bus Control: This is an internal arbiter shared by the PIO Control and DMA Control blocks. It schedules
the use of the main internal data paths.
DMA Control: Arbitrates and decodes requests from internal DMA sources (PBM, STC, IOMMU, MDU),
and arbitrates for the appropriate UPA FIFO.
Miscellaneous
Timer/Counter: Contains two identical 32-bit timer-counters as specied by the Sun-4U architecture. Used
for system scheduling and proling.
JTAG Control: Provides the necessary control for the standard IEEE 1149.1 JTAG port, as well as additional
scan based features that are useful for debugging purposes.
PCI Address Map Overview
Complete information on address maps and other software visible features of U2P can be found in the Pro-
grammer’s Model chapter of the U2P Users Manual. A simplied diagram showing PIO and normal DVMA
address spaces is in Figure 4.
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