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參數(shù)資料
| 型號： | STP2223BGA |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大小： | 476K |
| 代理商： | STP2223BGA |
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26
STP2223BGA
UPA to PCI Interface
U2P
July 1997
Note:
If the clock is stopped after the PLL is locked and the feedback loop is not broken, the PLL will go to
the low frequency state, i.e., 4-10MHz. If the clock recovers and resumes normal operation the PLL
will catch up with the input clock within 250
sec.
Note:
If the feedback loop is broken and the input frequency is higher than the feedback frequency, there will
be run-away i.e., PLL will go to high frequency state. The only way to recover is to bring BYPASS
up for 200
sec.
UPA Timing
A timing diagram is shown in Figure 6. as a reference for the data in the timing tables. UPA input and output
signals are referenced to the rising edge of UPA_CLKTiming Diagrams
Figure 6. Timing Waveforms
Clock
tHC
tLC
tRC
tFC
Clock
Input Signal
tSU
tH
Output Signal
tCO
1.5V
90%
10%
tcycle
Parameter Denitions
tSU: Required setup time of a chip input referenced to a given (clock) edge.
tH : Required hold time of a chip input referenced to a given (clock) edge.
tCO : Guaranteed propagation time of an output referenced to a given (clock) edge.
tVO: Guaranteed output hold time of an output referenced to a given (clock) edge.
tHC : Required clock high time.
tLC : Required clock low time.
tRC: Required clock rise time.
tFC: Required clock fall time.
tVO
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