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參數(shù)資料
| 型號： | STP2223BGA |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大小： | 476K |
| 代理商： | STP2223BGA |
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24
STP2223BGA
UPA to PCI Interface
U2P
July 1997
DC Characteristics
Environmental ELectrical Protection
AC Characteristics
All UPA inputs and outputs are referenced to the PECL clock input UPA_SYS_CLK + and UPA_SYS_CLK -.
This clock input also controls an on-chip Phase Lock Loop (PLL). All UPA inputs and outputs are clocked by
the rising edge of CLK + at the crossover between CLK +and CLK -, where both signals are at the same volt-
age. All UPA inputs are applied with a rise and fall time of 1.0 ns (nanosecond).
PCI inputs and outputs are referenced to PCIA_CLK and PCIB_CLK respectively.
Other U2P internal blocks run at the PSYCLOPS_CLK, which is xed at 66.7 MHz (15ns). There is a synchro-
nization boundary between the UPA interface block and other internal blocks.
TABLE 6: DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Vil
Input Low Voltage
TTL
0.8
V
PCI
-0.3
0.3 VDD
V
PECL
UPA_CLK, UPA_CLK_L
VDD -1.475
Vih
Input High Voltage
TTL
2.0
V
PCI
0.5VDD
VDD +0.5
V
PECL
UPA_CLK, UPA_CLK_L
VDD -1.165
Vol
Output Low Voltage
TTL
Iol = -4, -8, -16 mA
0.4
V
PCIA (DC)
Iol = 1.5 mA
0.1 VDD
V
PCIB (DC)
Iol = 6.0 mA
0.55
V
Voh
Output High Voltage
TTL
Ioh = -4, -8, -16 mA
2.4
V
PCIA (DC)
Ioh = - 0.5 mA
0.9 VDD
V
PCIB (DC)
Ioh = - 2.0 mA
2.4
V
Iin
Input Leakage
± 1
A
Ioz
Tri-state outputs
Voh = VSS or VDD
± 9
A
Cin
Input Capacitance
Any input/bidir buffer
2.5
6
pF
Cout
Output Capacitance
Any output buffer
2.5
6
pF
TABLE 7: Environmental Electrical Protection
ESD
Latch UP
Minimum
2KV
150 mA
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