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參數(shù)資料
| 型號： | STP1080ABGA-83 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 124K |
| 代理商： | STP1080ABGA-83 |
196
STP1080A
Companion Device for 167/200 MHz UltraSPARC-I Systems
UltraSPARC-I Data Buffer (UDB-I)
July 1997
Interrupt-Send Unit
UltraSPARC-I will be able to send interrupts. ASI stores will load data into a special UDB buffer. A nal ASI
store will initiate the interrupt. A status register in UltraSPARC-I can be read with an ASI load to interrogate
the completion status of the interrupt.
Control and Data Transfers
For UltraSPARC-I, the queue depth is generally one. UltraSPARC-I DataBuffer chips (UDB) have 64-byte buff-
ers reserved for each request class. Master Writes are the exception. To handle multiple noncacheable stores to
the frame buffer, this queue has eight entries. The UDB knows that only noncacheable stores use queue
entries besides the rst, and doesn’t require a full cache line of data buffering. Only 16 data bytes are used for
those queue entries.
Data transfers occur some arbitrary time after address requests. Masters are responsible for buffering all data
associated with queued requests.
Interrupt data delivery is handled as a normal System Controller (SC) write. (It is the only allowed SC write.
All other SC to UltraSPARC-I (SP) transactions must be SC reads).
The EcacheBus is controlled by the UltraSPARC-I ECU. Besides E-Cache reads and writes, there are transfers
to and from the UDB. UDBCntl[4:0] tells the UDB what’s happening on EcacheBus.
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