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參數(shù)資料
| 型號： | STP1080ABGA-83 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 124K |
| 代理商： | STP1080ABGA-83 |
DATA SHEET
191
STP1080A
UltraSPARC-I Data Buffer (UDB-I)
Companion Device for 167/200 MHz UltraSPARC-I Systems
DESCRIPTION
The UDB-I is a data buffer device used in UltraSPARC-I systems to connect the CPU and its external SRAM
cache bus to the system bus:
On the CPU/SRAM side, the E-Cache Bus consists of 128 data bits and 16 parity bits
On the system side, the UPA Bus consists of 128 data bits and 16 ECC bits
The UDB-I is clocked by the UPA clock; its interfaces are fully synchronous.
The UDB-I is a 256 pin, 3.3 volt CMOS device. It is an integral part of an UltraSPARC-I CPU system. In CPU
module based systems, the UDB-I is part of the module design.
The UDB-I device was originally called the “UDB”. The UDB-I device’s original part number was
STP1080BGA or simply STP1080. The “-I” sufx was added to the UDB reference to differentiate it from the
UDB-II, used in UltraSPARC-II designs.
The UDB-I part number was revised to STP1080A to reect a package change. The package thickness was
reduced from 2.4 mm to 2.19 mm. No other changes were made to its form, t, or function. The STP1080A is
designed to be a drop-in replacement for the STP1080.
Features
Benets
Isolates the processor from the system bus
High performance: ease of design
Interface to the UPA
Fully synchronous design
Operates at system frequency
Provides data buffering
Supports parity on the CPU side and ECC on the system
side
Stores interrupt vectors. Interrupt registers visible to
software
Enables secondary cache transfers and system memory
transfers by isolation
IEEE1149.1 (JTAG) boundary scan test
Ease of manufacturing test
256 PBGA package
Small footprint and cost effective packaging
July 1997
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