參數(shù)資料
型號: STMPE2401TBR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, PBGA36
封裝: LEAD FREE, TFBGA-36
文件頁數(shù): 36/55頁
文件大?。?/td> 959K
代理商: STMPE2401TBR
STMPE2401
Keypad controller
41/55
The keypad column inputs enabled by the KPC_col register are normally ‘HIGH’, with the
corresponding input pins pulled up by resistors internally. After reset, all the keypad row
outputs enabled by the KPC_row register are driven ‘LOW’. If a key is pressed, its
corresponding column input will become ‘LOW’ after making contact with the ‘LOW’ voltage
on its corresponding row output.
Once the key scan controller senses a ‘LOW’ input on any of the column inputs, the
scanning cycles will then start to determine the exact key that has been pressed. The twelve
row outputs will be driven ‘LOW’ one by one (if the row output is enabled) during each
scanning cycle. While one row is driven ‘LOW’, the other rows are driven ‘HIGH’. (The pull-
ups and pull-downs of row outputs are always disabled). If there is any column input sensed
as ‘LOW’ when a row is driven ‘LOW’, the key scan controller will then decode the key
coordinates (its corresponding row number and column number), save the key data into a
de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update
the key data into output data FIFO if valid.
13.1
Registers in keypad controller
Table 37. Register in keypad controller
Address
Register name
Description
Auto-Increment
(during sequential
R/W)
0x60
KPC_col
Keypad column scanning register
Yes
0x61
KPC_row_msb
Keypad row scanning register
Yes
0x62
KPC_row_lsb
Yes
0x63
KPC_ctrl_msb
Keypad control register
Yes
0x64
KPC_ctrl_lsb
Yes
0x68
KPC_data_byte0
Keypad data register
No
0x69
KPC_data_byte1
No
0x6A
KPC_data_byte2
No
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