參數(shù)資料
型號: STMPE2401TBR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, PBGA36
封裝: LEAD FREE, TFBGA-36
文件頁數(shù): 16/55頁
文件大小: 959K
代理商: STMPE2401TBR
STMPE2401
Interrupt system
23/55
9.2
Interrupt control register (ICR)
ICR register is used to configure the Interrupt Controller. It has a global enable interrupt
mask bit that controls the interruption to the host.
9.3
Interrupt enable mask register (IER)
IER register is used to enable the interruption from a particular interrupt source to the host.
ICR_msb
ICR_lsb
Bit
151413
121110
9
8
7
6
5
4
3
2
1
0
Reserved
IC2
IC1
IC0
R/W
R
RRR
RR
R
RW
Reset
Value
0
00
000
00
0
Table 21. ICR
Bits
Name
Description
0
IC[0]
Global Interrupt Mask bit
When this bit is written a ‘1’, it will allow interruption to the host. If it is written
with a ‘0’, then, it disables all interruption to the host. Writing to this bit does not
affect the IER value.
1
IC[1]
output Interrupt Type
‘0’ = Level interrupt
‘1’ = Edge interrupt
2
IC[2]
output Interrupt Polarity
‘0’ = Active Low / Falling Edge
‘1’ = Active High / Rising Edge
IER_msb
IER_lsb
Bit
15
14
13
12
11
10
9
8
7
6
543
21
0
Reserved
IE8
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
R/W
R
RW
Reset
Value
0
00
000
00
0
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