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參數(shù)資料
| 型號： | STM32W108HBU7 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40 |
| 文件頁數(shù)： | 120/198頁 |
| 文件大?。?/td> | 2871K |
| 代理商： | STM32W108HBU7 |
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Embedded memory
STM32W108CB, STM32W108HB
Doc ID 16252 Rev 3
4.1
Flash memory
The STM32W108 provides a total of 130.5 kB of flash memory in three separate blocks:
●
Main Flash Block (MFB)
●
Fixed Information Block (FIB)
●
Customer Information Block (CIB)
The MFB is divided into 128 1024-byte pages. The CIB is a single 512-byte page. The FIB is
a single 2048-byte page. The smallest erasable unit is one page and the smallest writable
unit is an aligned 16-bit half-word. The flash is rated to have a guaranteed 1,000 write/erase
cycles. The flash cell has been qualified for a data retention time of >100 years at room
temperature.
Flash may be programmed either through the Serial Wire/JTAG interface or through
bootloader software. Programming flash through Serial Wire/JTAG requires the assistance
of RAM-based utility code. Programming through a bootloader requires specific software for
over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also
available preprogrammed into the FIB.
4.2
Random-access memory
The STM32W108 has 8 kbytes of static RAM on-chip. The start of RAM is mapped to
address 0x20000000. Although the ARM Cortex-M3 allows bit band accesses to this
address region, the standard MPU configuration does not permit use of the bit-band feature.
The RAM is physically connected to the AHB System bus and is therefore accessible to both
the ARM Cortex-M3 microprocessor and the debugger. The RAM can be accessed for
both instruction and data fetches as bytes, half words, or words. The standard MPU
configuration does not permit execution from the RAM, but for special purposes, such as
programming the main flash block, the MPU may be disabled. To the bus, the RAM appears
as 32-bit wide memory and in most situations has zero wait state read or write access. In
the higher CPU clock mode the RAM requires two wait states. This is handled by hardware
transparent to the user application with no configuration required.
4.2.1
Direct memory access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data
into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general
purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full
duplex so that a read and a write to RAM may be requested at the same time. Thus there
are six DMA channels in total.
The STM32W108 integrates a DMA arbiter that ensures fair access to the microprocessor
as well as the peripherals through a fixed priority scheme appropriate to the memory
bandwidth requirements of each master. The priority scheme is as follows, with the top
peripheral being the highest priority:
1.
General Purpose ADC
2.
Serial Controller 2 Receive
3.
Serial Controller 2 Transmit
4.
MAC
5.
Serial Controller 1 Receive
6.
Serial Controller 1 Transmit
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