參數(shù)資料
型號: STE2001DIE1
廠商: 意法半導(dǎo)體
英文描述: 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
中文描述: 65 × 128單芯片LCD控制器/驅(qū)動
文件頁數(shù): 7/36頁
文件大?。?/td> 326K
代理商: STE2001DIE1
7/36
STE2001
CIRCUITDESCRIPTION
SuppliesVoltages and Grounds
V
DD2
and V
DD3
are supply voltagesto the internalvoltage generator (see below). They must be externally connected.
If the internal voltagegenerator is not used, these should be connectedto V
DD1
pad. V
DD1
supplies the rest of the IC.
This supply voltage could be different form V
DD2
and V
DD3
. V
DD1
must be lower than V
DD2,3
+ 0.5V.
InternalSupply Voltage Generator
The IC has a fully integrated (no external capacitors required)charge pump for the LiquidCrystal Display supply volt-
age generation. The multiplying factor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplication’
Command. The output voltage (V
LCDOUT
) is tightly controlled through the V
LCDSENSE
pad. For this voltage, four dif-
ferent temperature coefficients(TC, rateof changewithtemperature)can be programmed using the bits TC1 and TC0.
This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the V
LCDIN
and V
LCDOUT
pads must be connected together. An external supply could be connected to V
LCDIN
to supply the LCD
without using the internal generator.In such event the V
LDCOUT
and V
LCDSENSE
must be connected to GND and the
internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the DisplaySystem.
WhenusedtheOSCpadmustbeconnectedtoVDD1pad.AnexternaloscillatorcouldbeusedandfedintotheOSCpin.
DisplayData RAM
The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to
Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accom-
plished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal)
and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:
Normal Horizontal (MX = 0 and V = 0), having the columnwith address X = 0 located on the left of the memory map.
The Xpointerisincreased aftereach byte written. After the last columnaddress (X = 127), Y address pointer is mod-
ified to jump to next row. X restarts from X = 0 (Fig.2).
Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 3).
Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory
map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer
is modified to jump to nextrow. X restarts from X = 0 (fig. 4).
Mirrored Vertical (MX =1 and V = 1), having the columnwith address X = 0 located on the right of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 5).
After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0).Data
bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7).
Mux 65 Mode
The STE2001 provides also means to alter the normal output addressing.A mirroring of the Display along the X axis
is enabled setting to a logic one the MY bit. This function is achieved reading the matrix from physical row 63 to 0,
since the relation between the physical memory rows and the output row drivers is only dependent on the memory
reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of
the memory map. It is only related to the visualizationprocess (Fig. 8 & Fig. 9).
It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axisof
each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the
Interface Pads are located),setting the TRS bitto a logic one, and on the Row Pads locatedon the otheredge, setting
the BRS bit to a logic one.
Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic
data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
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