參數(shù)資料
型號(hào)： ST72F651AR6T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 61/161頁
文件大?。?/td> 2656K
代理商： ST72F651AR6T1
ST72651AR6
153/161
Doc ID 7215 Rev 4
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH). FLASH devices are
shipped to customers with a default content (FFh).
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes.
15.1 OPTION BYTE
The option byte allows the hardware configuration
of the microcontroller to be selected.
The option byte has no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh. This means that all the options have
“1” as their default value.
OPT7 = Reserved. Must be kept at 1.
OPT6 = PE5PU I/O Port PE5 Pull-up Option
This option bit determines if a pull-up is connected
on Port E5.
0: Pull up present on PE5
1: No pull-up on PE5
When PE5PU=00, (also refer to Table 38):
– For input, software can enable or disable the
pull-up by programming PEOR.5 and PED-
DR.5=0.
– For output, the pull-up is enabled when Open
Drain is selected by programming PEOR.5= and
PEDDR.5=1.
Table 38. PE5PU Options
OPT5:4 = PSMOD[1:0] Power Supply Mode
These option bits configure the power supply
mode. Refer to Table 39 for more information.
Table 39. Power supply bits
OPT3 = Reserved. Must be kept at 1.
OPT2= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT1 = USBEN
0: USBEN alternate function disabled. Port F4 is
free for general purpose I/O
1: USBEN alternate function enabled on Port F4
(function controlled by hardware)
OPT0= FMP_R Flash memory read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
This protection is based on read and a write pro-
tection of the memory in test modes and IAP.
70
-
PE5
PU
PS
MOD1
PS
MOD0
-
WDG
SW
USB
EN
FMP_
R
Configuration
PE5PU
OPTION
PEOR.5
PEDDR.5
Input floating
0
00
Output Open Drain
with Pull-up
01
Input with pull-up
1
0
Output push pull
1
Input floating
1
00
Output Open Drain
0
1
Input floating
1
0
Output push pull
1
Mode
USB
Voltage
Detector
PLL
OPT5 OPT4
Forced Stand-
alone mode
Ignored
Not Started
0
Normal Dual-
Supply mode
Read
Determined
by detector
value
x1
Forced USB
mode
Ignored
Started
1
0
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