參數(shù)資料
型號: ST72F651AR6T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù): 121/161頁
文件大小: 2656K
代理商: ST72F651AR6T1
ST72651AR6
62/161
Doc ID 7215 Rev 4
USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
There are five bidirectional Endpoints including
one control Endpoint 0. Endpoint 1 and Endpoint 2
are counted as 4 bulk or interrupt Endpoints (two
IN and two OUT).
Endpoint 0 and Endpoint 1 are both 2 x 16 bytes in
size. Endpoint 2 is 2 x 64 bytes in size and can be
configured to physically target different USB Data
Buffer areas depending on the MOD[1:0] bits in
the CTLR register (see Figure 37, Figure 38 and
The USB Data Buffer operates as a double buffer;
while one 512-byte block is being read/written by
the DTC, the USB interface reads/writes the other
512-byte block.
The management of the data transfer is performed
in upload and download mode (2 x 512 byte buff-
ers for Endpoint 2) by the USB Data Buffer Manag-
er.
Figure 37. Endpoint 2 Normal Mode selected by (MOD[1:0] Bits = 00h)
Figure 38. Endpoint 2 Download Mode selected by MOD[1:0] Bits = 10b
Endpoint 2 Buffer OUT
Endpoint 1 Buffer IN
Endpoint 1 Buffer OUT
Endpoint 0 Buffer IN
Endpoint 0 Buffer OUT
Endpoint 2 Buffer IN
16 Bytes
64 Bytes
1550h
155Fh
156Fh
157Fh
158Fh
15CFh
160Fh
USB DATA
512-byte buffer
as 64-byte slices
512-byte buffer
as 64-byte slices
64-byte buffer
1650h
1A4Fh
15CFh
Endpoint 2 Buffer IN
Endpoint 2 Buffer OUT
158Fh
1550h
Endpoint 1 Buffer OUT
Endpoint 1 Buffer IN
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
1590h
1
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