參數(shù)資料
型號(hào): ST72F651AR6T1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件頁數(shù): 12/161頁
文件大?。?/td> 2656K
代理商: ST72F651AR6T1
ST72651AR6
109/161
Doc ID 7215 Rev 4
IC SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.5 Low Power Modes
11.7.6 Interrupts
Figure 65. Event Flags and Interrupt Generation
Note: The I2C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bits in the CC
register are reset (RIM instruction).
Mode
Description
WAIT
No effect on I2C interface.
I2C interrupts cause the device to exit from WAIT mode.
HALT
I2C registers are frozen.
In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
End of Byte Transfer Event
BTF
ITE
Yes
No
Start Bit Generation Event (Master mode)
SB
Yes
No
Acknowledge Failure Event
AF
Yes
No
BTF
SB
AF
EVF
INTERRUPT
ITE
*
* EVF can also be set by EV2 or an error from the SR2 register.
*
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