參數(shù)資料
型號(hào): ST72F60E1M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁數(shù): 132/139頁
文件大小: 1993K
代理商: ST72F60E1M1
USB interface (USB)
ST7260xx
92/139
Bit 2 = RX_SEZ Received single-ended zero
This bit indicates the status of the RX_SEZ transceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
Bit 1 = RXD Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver output (differential receiver output).
Note:
If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the
application. By interpreting the status, software can distinguish a valid End Suspend event
from a spurious wake-up due to noise on the external USB line. A valid End Suspend is
followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is
indicated by RX_SEZ=1.
Bit 0 = Reserved. Forced by hardware to 0.
14.4.4
Interrupt status register (ISTR)
When an interrupt occurs these bits are set by hardware. Software must read them to
determine the interrupt type and clear them after servicing.
Note:
These bits cannot be set by software.
Bit 7 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle state is present on the bus line for more
than 3 ms, indicating a suspend mode request from the USB bus. The suspend request
check is active immediately after each USB reset event and its disabled by hardware when
suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence.
Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor can’t answer a DMA request in time.
0: No over/underrun detected
1: Over/underrun detected
Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is
performed. The type of transfer can be determined by looking at bits TP3-TP2 in register
PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register
IDR.
0: No Correct Transfer detected
1: Correct Transfer detected
Note:
A transfer where the device sent a NAK or STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is considered correct if there are no errors in
the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data
overruns, bit stuffing or framing errors.
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the errors listed below has occurred:
ISTR
Reset value:
0000 0000 (00h)
76
543
21
0
SUSP
DOVR
CTR
ERR
IOVR
ESUSP
RESET
SOF
R/W
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