參數(shù)資料
型號: ST72F60E1M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件頁數(shù): 112/139頁
文件大小: 1993K
代理商: ST72F60E1M1
Serial communications interface (SCI)
ST7260xx
74/139
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 38).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 39.
Word length programming
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character Transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 38).
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Start
Bit
Stop
Bit
Next
Start
Bit
Idle Frame
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Stop
Bit
Next
Start
Bit
Start
Bit
Idle Frame
Start
Bit
9-bit Word length (M bit is set)
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Possible
Parity
Bit
Break Frame
Start
Bit
Extra
’1’
Data Frame
Break Frame
Start
Bit
Extra
’1’
Data Frame
Next Data Frame
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