參數(shù)資料
型號(hào): SST89E564RD-40-I-PJ
廠(chǎng)商: Silicon Storage Technology, Inc.
英文描述: FlashFlex51 MCU
中文描述: FlashFlex51單片機(jī)
文件頁(yè)數(shù): 43/62頁(yè)
文件大?。?/td> 680K
代理商: SST89E564RD-40-I-PJ
Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
43
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
8.0 PROGRAMMABLE COUNTER ARRAY (PCA)
The device is equipped with an integrated Program
Counter Array (PCA). The PCA consists of a dedicated
timer/counter that serves as the common time base for an
array of 5 compare/capture modules. Each of the modules
can be programmed in 1 of 4 modes. Additionally, the 5th
module can be programmed as a Watchdog Timer.
8.1 PCA Timer/Counter
The timer/counter for the PCA is a free-running 16 timer
and consists of registers CH and CL (the high and low
bytes of the count values). These registers can be read and
written to at any time. The Count Pulse Select bits (CPS1 &
CPS0) in the CMOD register configure the timer/counter to
operate in 1 of 4 modes. See Table 8-1. The CMOD regis-
ter also contains the Counter Idle (CIDL) bit. When CIDL =
1 the PCA timer/counter will be turned off when the MCU
enters Idle Mode
.
TABLE
The Counter Run bit (CR) in CCON register turns the timer/
counter on and off. When CR = 1 the timer/counter is run-
ning and when CR = 0 the timer/counter will be disabled.
When the PCA timer/counter overflows the CF bit in CCON
register will be set and if the ECF bit in CMOD register is
set an interrupt will be generated.
8.2 PCA Compare/Capture Modules
Each of the 5 Compare/Capture modules has a mode reg-
ister called CCAPMn (n = 0, 1, 2, 3, or 4) which selects the
function it will perform. The seven possible modes and their
associated values for CCAPMn are shown in Table 8-2.
Additionally each of the five modules has two 8-bit capture/
compare registers (CCAPnH & CCAPnL) and an external
input/output pin associated with it. The external input/output
pins are P1.3 for Module 0, P1.4 for Module 1, P1.5 for
Module 2, P1.6 for Module 3 and P1.7 for Module 4. Each
module also has an associated event flag CCFn located in
CCON register. These flags must be cleared by software.
Writing to CCAPnL will disable the compare feature of the
corresponding module and writing to CCAPnH will re-
enable it. Therefore, when using the compare feature (16-
Bit Software Timer, High Speed Output, Pulse Width Mod-
ulator & Watchdog Timer modes) the software should
always write to CCAPnL first and then write to CCAPnH
second.
8.2.1 Capture Mode
Capture Mode is used to capture the PCA timer/counter
value into a module’s capture registers (CCAPnH &
CCAPnL). The capture will occur on a positive edge, a neg-
ative edge or both edges of the input signal on the corre-
sponding external input pin depending on which mode is
selected. Also, the event flag (CCFn) is set and an interrupt
is generated if ECCFn is set.
8-1: C
OUNT
P
ULSE
S
ELECTED
B
ITS
CPS1
0
0
1
1
CPS0
0
1
0
1
PCA Count Pulse Selected
Internal Clock, FOSC / 12
Internal Clock, FOSC / 4
Timer 0 Overflow
External Clock at P1.2
T8-1.0 555
TABLE
8-2: P
OSSIBLE
M
ODES
AND
A
SSOCIATED
V
ALUES
FOR
CCAPM
N
Module Function
Capture Positive Edge Only
Capture Negative Edge Only
Capture Both Edges
16-Bit Software Timer
High Speed Output
Pulse Width Modulator
Watchdog Timer
1
CCAPMn Value
without
interrupt
enabled
20H
10H
30H
48H
4CH
42H
48H or 4CH
with
interrupt
enabled
21H
11H
31H
49H
4DH
43H
-
T8-2.0 555
1. Only for Module 4
相關(guān)PDF資料
PDF描述
SST89E564RD-40-I-TQI FlashFlex51 MCU
SST89E564RD-40-I-TQJ FlashFlex51 MCU
SST89V554RC FlashFlex51 MCU
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SST89V554RC-40-C-NJ FlashFlex51 MCU
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