參數(shù)資料
型號: SST89E564RD-40-I-PJ
廠商: Silicon Storage Technology, Inc.
英文描述: FlashFlex51 MCU
中文描述: FlashFlex51單片機(jī)
文件頁數(shù): 42/62頁
文件大小: 680K
代理商: SST89E564RD-40-I-PJ
42
Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDT) * 344064 * 1/f
OSC
where WDT is the value loaded into the WDT register and
f
OSC
is the oscillator frequency.
FIGURE
7-1: B
LOCK
D
IAGRAM
OF
P
ROGRAMMABLE
W
ATCHDOG
T
IMER
555 ILL F18.0
WDT Upper Byte
WDT Reset
Internal Reset
344064
clks
Counter
CLK (XTAL1)
Ext. RST
WDTC
WDTD
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SST89E564RD-40-I-QIF 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex MCU
SST89E564RD-40-I-TQI 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU
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