參數(shù)資料
型號(hào): SST89E564RD-40-I-PJ
廠商: Silicon Storage Technology, Inc.
英文描述: FlashFlex51 MCU
中文描述: FlashFlex51單片機(jī)
文件頁(yè)數(shù): 24/62頁(yè)
文件大?。?/td> 680K
代理商: SST89E564RD-40-I-PJ
24
Preliminary Specifications
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
2001 Silicon Storage Technology, Inc.
S71207-00-000
9/01
555
Symbol
SPIE
SPE
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, f
OSC
, is as follows:
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Symbol
SPIF
Function
Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt
is then generated. To clear, read SPSR and then access SPDR.
Set if the SPI data register is written to during data transfer. To clear, read SPSR and
then access SPDR.
WCOL
SPI Control Register (SPCR)
Location
D5H
7
6
5
4
3
2
1
0
Reset Value
00000100b
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = f
OSC
divided by
4
16
64
128
SPI Status Register (SPSR)
Location
AAH
7
6
5
-
4
-
3
-
2
-
1
-
0
-
Reset Value
00xxxxxxb
SPIF
WCOL
相關(guān)PDF資料
PDF描述
SST89E564RD-40-I-TQI FlashFlex51 MCU
SST89E564RD-40-I-TQJ FlashFlex51 MCU
SST89V554RC FlashFlex51 MCU
SST89V554RC-40-C-NI FlashFlex51 MCU
SST89V554RC-40-C-NJ FlashFlex51 MCU
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