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參數(shù)資料
| 型號： | SST31LF041-300-4E-WH |
| 廠商： | Silicon Storage Technology, Inc. |
| 元件分類： | 組合存儲器 |
| 英文描述： | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| 中文描述： | 4 Mbit閃存1兆位或256千位的SRAM ComboMemory |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 294K |
| 代理商： | SST31LF041-300-4E-WH |
4
Data Sheet
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01 392
after the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 7 for Data# Polling timing diagram and Figure 17 for
a flowchart.
Flash Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BE#) pulse for Program operation. For Sec-
tor or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 8 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
Flash Memory Data Protection
The SST31LF021/021E flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST31LF021/021E provide the JEDEC approved
Software Data Protection scheme for all flash memory
bank data alteration operations, i.e., Program and Erase.
Any Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST31LF021/021E devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid SDP commands will abort the device to
the Read mode, within T
RC.
Concurrent Read and Write Operations
The SST31LF021/021E provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the flash. The device will
ignore all SDP commands when an Erase or Program
operation is in progress. This allows data alteration code to
be executed from SRAM, while altering the data in flash.
The following table lists all valid states. SST does not rec-
ommend that both bank enables, BEF# and BES#, be
simultaneously asserted.
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
Product Identification
The Product Identification mode identifies the devices as
either SST31LF021 or SST31LF021E and the manufac-
turer as SST. This mode may be accessed by hardware or
software operations. The hardware device ID Read opera-
tion is typically used by a programmer to identify the correct
algorithm for the SST31LF021/021E flash memory banks.
Users may wish to use the software Product Identification
operation to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For
details, see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the software ID entry and
read timing diagram and Figure 18 for the ID entry com-
mand sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
SRAM
Read
Write
Program/Erase
Program/Erase
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
0000H
Data
BFH
Manufacturer’s ID
Device ID
SST31LF021
SST31LF021E
0001H
0001H
18H
19H
T1.4 392
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST31LF041-300-4E-WI | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4C-WH | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4C-WI | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4E-WH | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4E-WI | 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST31LF041-300-4E-WI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4C-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
| SST31LF041-70-4C-WI | 功能描述:閃存 4M FLASH 1M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST31LF041-70-4C-WIE | 功能描述:閃存 4M FLASH 1M SRAM RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| SST31LF041-70-4E-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory |
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