參數(shù)資料
型號： SPAK56F807VF80
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝： MOLD ARRAY PROCESS, BGA-160
文件頁數(shù)： 7/48頁
文件大小： 853K
代理商： SPAK56F807VF80
Quad Timer Module Signals
MOTOROLA
DSP56F807 Preliminary Technical Data
15
2.13 Quad Timer Module Signals
2.14 JTAG/OnCE
1
VREF2
Input
VREF2—Analog reference voltage for ADC. Must be set to
VDDA-0.3V for optimal performance.
Table 18. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal Type
State During
Reset
Signal Description
2
TC0-1
Input/Output
Input
TC0-1—Timer C Channels 0 and 1
4
TD0-3
Input/Output
Input
TD0-3—Timer D Channels 0, 1, 2, and 3
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
Input, pulled
low internally
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
1
TMS
Input
Input, pulled
high internally
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
1
TDI
Input
Input, pulled
high internally
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
1
TRST
Input
Input, pulled
high internally
Test Reset—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment
when a hardware DSP reset is required and it is necessary not to
reset the OnCE/JTAG module. In this case, assert RESET, but
do not assert TRST.
1
DE
Output
Debug Event—DE provides a low pulse on recognized debug
events.
Table 17. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
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