參數(shù)資料
型號(hào): SPAK56F807VF80
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁數(shù): 30/48頁
文件大?。?/td> 853K
代理商: SPAK56F807VF80
36
DSP56F807 Preliminary Technical Data
MOTOROLA
.
Figure 28. Equivalent Analog Input Circuit
1.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. 2.04pf
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms
4.
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is
only connected to it at sampling time. 1pf
5.
3.13 Controller Area Network (CAN) Timing
Table 37. CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF,
MSCAN Clock = 30 MHz
Figure 29. Bus Wakeup Detection
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BRCAN
1Mbps
Bus Wakeup detection 1
1.
If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any
bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus
wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds
originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1
Mbps.
2.
Parameters listed are guaranteed by design
T WAKEUP
5
us
1
2
3
4
ADC analog input
T WAKEUP
MSCAN_RX
CAN receive
data pin
(Input)
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