參數(shù)資料
型號(hào)： SPAK56F807VF80
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝： MOLD ARRAY PROCESS, BGA-160
文件頁(yè)數(shù)： 2/48頁(yè)
文件大?。?/td> 853K
代理商： SPAK56F807VF80
10
DSP56F807 Preliminary Technical Data
MOTOROLA
2.5 Interrupt and Program Control Signals
Table 9. Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
PS
Output
Tri-stated
Program Memory Select—PS is asserted low for external program
memory access.
1
DS
Output
Tri-stated
Data Memory Select—DS is asserted low for external data
memory access.
1
WR
Output
Tri-stated
Write Enable—WR is asserted during external memory write
cycles. When WR is asserted low, pins D0–D15 become outputs
and the DSP puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0–A15, PS, and DS pins. WR can be
connected directly to the WE pin of a Static RAM.
1
RD
Output
Tri-stated
Read Enable—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an
external device is enabled onto the DSP data bus. When RD is
deasserted high, the external data is latched inside the DSP. When
RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be
connected directly to the OE pin of a Static RAM or ROM.
Table 10. Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
IRQA
Input
External Interrupt Request A—The IRQA input is a
synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to
be level-sensitive or negative-edge-triggered.
1
IRQB
Input
External Interrupt Request B—The IRQB input is an external
interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive
or negative-edge-triggered.
1
RSTO
Output
Reset Output—This output reflects the internal reset state of
the chip.
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