參數(shù)資料
型號(hào): SPAK56F807VF80
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁(yè)數(shù): 24/48頁(yè)
文件大?。?/td> 853K
代理商: SPAK56F807VF80
30
DSP56F807 Preliminary Technical Data
MOTOROLA
3.8 Serial Peripheral Interface (SPI) Timing
1.
Parameters listed are guaranteed by design.
Table 32. SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF, fOP = 80MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
50
25
ns
Figures 20-23
Enable lead time
Master
Slave
tELD
25
ns
Figure 23
Enable lag time
Master
Slave
tELG
100
ns
Figure 23
Clock (SCK) high time
Master
Slave
tCH
17.6
12.5
ns
Figures 20, 21,
Clock (SCK) low time
Master
Slave
tCL
24.1
25
ns
Figure 23
Data setup time required for inputs
Master
Slave
tDS
20
0
ns
Figures 20, 21,
Data hold time required for inputs
Master
Slave
tDH
0
2
ns
Figures 20, 21,
Access time (time to data active from high-
impedance state)
Slave
tA
4.8
15
ns
Figure 23
Disable time (hold time to high-impedance state)
Slave
tD
3.7
15.2
ns
Figure 23
Data Valid for outputs
Master
Slave (after enable edge)
tDV
4.5
20.4
ns
Figures 20, 21,
Data invalid
Master
Slave
tDI
0
ns
Figures 20, 21,
Rise time
Master
Slave
tR
11.5
10.0
ns
Figures 20, 21,
Fall time
Master
Slave
tF
9.7
9.0
ns
Figures 20, 21,
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