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參數(shù)資料
| 型號： | SPAK56F807VF80 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PBGA160 |
| 封裝： | MOLD ARRAY PROCESS, BGA-160 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大小： | 853K |
| 代理商： | SPAK56F807VF80 |
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DSP56F807 Description
MOTOROLA
DSP56F807 Preliminary Technical Data
3
Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D
with four pins
CAN 2.0 B Module with 2-pin port for transmit and receive
Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)
Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
Computer-Operating Properly (COP) Watchdog timer
Two dedicated external interrupt pins
14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
External reset input pin for hardware reset
External reset output pin for system reset
JTAG/On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
1.2 DSP56F807 Description
The DSP56F807 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F807 is well-suited for many applications.
The DSP56F807 includes many peripherals that are especially useful for applications such as motion
control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial control for
power, lighting, and automation.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model
and optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The DSP56F807 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The DSP56F807 also provides two
external dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The DSP56F807 DSP controller includes 60K, 16-bit words of program flash and 8K words of data flash
(each programmable through the JTAG port) with 2K words of program RAM and 4K words of data RAM.
It also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
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