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參數(shù)資料
| 型號： | SPAK56F802TA60 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 60 MHz, OTHER DSP, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 573K |
| 代理商： | SPAK56F802TA60 |
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10
56F802 Technical Data
MOTOROLA
2.7 Quad Timer Module Signals
2.8 JTAG/OnCE
Table 10. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
2
TD1-2
GPIOA1-2
Input/
Output
Input/
Output
Input
TD1-2—Timer D Channel 1-2
Port A GPIO—These pins are General Purpose I/O (GPIO)
pins that can be individually programmed as input or output
pins.
After reset, the default state is the quad timer input.
Table 11. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
(Schmitt)
Input, pulled
low internally
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
1
TMS
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
1
TDI
Input
(Schmitt)
Input, pulled
high internally
Test Data Input—This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
1
TRST
Input
(Schmitt)
Input, pulled
high internally
Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted at power-up and whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the OnCE/JTAG module is under the control of the debugger. In
this case it is not necessary to assert TRST when asserting RESET.
Outside of a debugging environment RESET should be permanently
asserted by grounding the signal, thus disabling the OnCE/JTAG
module on the device.
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