參數(shù)資料
型號(hào)： SPAK56F802TA60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 60 MHz, OTHER DSP, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 18/39頁(yè)
文件大?。?/td> 573K
代理商： SPAK56F802TA60
JTAG Timing
MOTOROLA
56F802 Technical Data
25
Figure 15. Equivalent Analog Input Circuit
1.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing.
(2.04pf)
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4.
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the
input and is only connected to it at sampling time. (1pf)
3.10 JTAG Timing
Table 25. JTAG Timing 1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF
1.
Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
2.
TCK frequency of operation must be less than 1/8 the processor rate.
3.
Parameters listed are guaranteed by design.
fOP
DC
10
MHz
TCK cycle time
tCY
100
—
ns
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data setup time
tDS
0.4
—
ns
TMS, TDI data hold time
tDH
1.2
—
ns
TCK low to TDO data valid
tDV
—
26.6
ns
TCK low to TDO tri-state
tTS
—
23.5
ns
TRST assertion time
tTRST
50
—
ns
1
2
3
4
ADC analog input
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