參數(shù)資料
型號(hào)： SPAK56F802TA60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 60 MHz, OTHER DSP, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 15/39頁(yè)
文件大?。?/td> 573K
代理商： SPAK56F802TA60
22
56F802 Technical Data
MOTOROLA
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Figure 11. External Level-Sensitive Interrupt Timing
3.7 Quad Timer Timing
Table 21. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
RESET Assertion to Address, Data and Control Signals High
Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
3.
Parameters listed are guaranteed by design.
tRA
275,000T
128T
—
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
Table 22. Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
1.
In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
Timer input period
PIN
4T+6
—
ns
Timer input high/low period
PINHL
2T+3
—
ns
Timer output period
POUT
2T
—
ns
Timer output high/low period
POUTHL
1T
—
ns
General
Purpose
I/O Pin
IRQA
b) General Purpose I/O
tIG
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