參數(shù)資料
型號： SPAK56F802TA60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 60 MHz, OTHER DSP, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁數(shù)： 1/39頁
文件大?。?/td> 573K
代理商： SPAK56F802TA60
DSP56F802/D
Rev. 4.0, 08/2003
Motorola, Inc., 2003. All rights reserved.
56F802
Technical Data
56F802 16-bit Hybrid Controller
Up to 30 MIPS operation at 60MHz core
frequency
Up to 40 MIPS operation at 80MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
Hardware DO and REP loops
6-channel PWM Module with fault input
Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
Serial Communications Interface (SCI)
8K
× 16-bit words Program Flash
1K
× 16-bit words Program RAM
2K
× 16-bit words Data Flash
1K
× 16-bit words Data RAM
2K
× 16-bit words Boot Flash
Two General Purpose Quad Timers with 2
external outputs
JTAG/OnCETM port for debugging
4 shared GPIO
On-chip relaxation oscillator
32-pin LQFP Package
Figure 1. 56F802 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
→ 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
COP/
Watchdog
SCI0
or
GPIO
Quad Timer D
or GPIO
Quad Timer C
A/D1
A/D2
ADC
2
3
2
6
PWM Outputs
PWMA
16
VCAPC
VDD
VSS*VDDA
VSSA
5
22
3
VREF
PLL
Relaxation
Oscillator
.
*includes TCS pin which is reserved for factory use and is tied to VSS
Fault A0
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