參數(shù)資料
型號(hào): SPAK56F802TA60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 60 MHz, OTHER DSP, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁數(shù): 17/39頁
文件大?。?/td> 573K
代理商: SPAK56F802TA60
24
56F802 Technical Data
MOTOROLA
3.9 Analog-to-Digital Converter (ADC) Characteristics
Table 24. ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14,(for optimal
performance), ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL 50pF
Characteristic
Symbol
Min
Typ
Max
Unit
ADC input voltages
VADCIN
01
1.
For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert
to a digital output code of 0.
VREF
2
2.
VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF
to VDDA-0.3V.
V
Resolution
RES
12
12
Bits
Integral Non-Linearity3
3.
Measured in 10-90% range.
INL
+/- 4
+/- 5
LSB4
4.
LSB = Least Significant Bit.
Differential Non-Linearity
DNL
+/- 0.9
+/- 1
LSB3
Monotonicity
GUARANTEED
ADC internal clock5
5.
Guaranteed by characterization.
fADIC
0.5
5MHz
Conversion range
RAD
VSSA
VDDA
V
Power-up time
tADPU
2.5
msec
Conversion time
tADC
6
tAIC cycles
6
6.
tAIC = 1/fADIC
Sample time
tADS
1
tAIC cycles
6
Input capacitance
CADI
5
pF6
Gain Error (transfer gain)5
EGAIN
1.00
1.10
1.15
Offset Voltage5
VOFFSET
+10
+230
+325
mV
Total Harmonic Distortion5
THD
55
60
dB
Signal-to-Noise plus Distortion5
SINAD
54
56
——
Effective Number of Bits5
ENOB
8.5
9.5
bit
Spurious Free Dynamic Range5
SFDR
60
65
dB
Spurious Free Dynamic Range
SFDR
65
70
dB
ADC Quiescent Current (both ADCs)
IADC
50
mA
VREF Quiescent Current (both ADCs)
IVREF
12
16.5
mA
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