參數(shù)資料
型號： SNJ54LVT8986HV
廠商： Texas Instruments, Inc.
英文描述： 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
中文描述： 3.3 V的連接尋址掃描港口多點尋址IEEE標(biāo)準(zhǔn)1149.1（JTAG接口）技術(shù)咨詢收發(fā)器
文件頁數(shù)： 9/51頁
文件大?。?/td> 880K
代理商： SNJ54LVT8986HV
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE 2
(secondary TAP configuration using bypass inputs) (continued)
INPUTS
LINKING SHADOW
PROTOCOL
RESULT
OUTPUTS
BYP5
–
0
PTRST
STRST
2
–
0
STCK
2
–
0
STMS2
STMS1
STMS0
STDO2
STDO1
STDO0
PTDO
CTDO
L L H H H H
H
–
H
PTCK
STMS2
STMS2
STMS2
STMS2
PTMS
STMS1
STMS1
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
Z
Z
Z
Z
CTDI
L L H H H L
H
–
H
PTCK
Z
Z
PTDI
Z
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
L L H H L H
H
–
H
PTCK
Z
PTDI
Z
Z
L L H H L L
H
–
H
PTCK
PTMS
STMS1
STMS1
PTMS
Z
STDI0
Z
PTDI
Z
L L H L H H
H
–
H
PTCK
PTDI
Z
Z
L L H L H L
H
–
H
PTCK
PTMS
STDI0
STDI1
STDI1
Z
PTDI
Z
L L H L L H
H
–
H
PTCK
PTMS
PTDI
Z
Z
L L H L L L
H
–
H
PTCK
PTMS
PTMS
STDI0
PTDI
Z
L H L H H H
H
–
H
PTCK
STMS2
STMS2
STMS2
STMS2
PTMS
STMS1
STMS1
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
Z
Z
Z
Z
CTDI
L H L H H L
H
–
H
PTCK
Z
Z
CTDI
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
L H L H L H
H
–
H
PTCK
Z
CTDI
Z
L H L H L L
H
–
H
PTCK
PTMS
STMS1
STMS1
PTMS
Z
STDI0
Z
CTDI
L H L L H H
H
–
H
PTCK
CTDI
Z
L H L L H L
H
–
H
PTCK
PTMS
STDI0
STDI1
STDI1
Z
CTDI
L H L L L H
H
–
H
PTCK
PTMS
CTDI
Z
L H L L L L
H
–
H
PTCK
PTMS
PTMS
STDI0
CTDI
L H H H H H
H
–
H
PTCK
STMS2
STMS2
STMS2
STMS2
PTMS
STMS1
STMS1
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
STMS0
PTMS
Z
Z
Z
Z
CTDI
L H H H H L
H
–
H
PTCK
Z
Z
CTDI
Z
STDI0
STDI1
STDI1
STDI2
STDI2
STDI2
STDI2
L H H H L H
H
–
H
PTCK
Z
CTDI
Z
Z
L H H H L L
H
–
H
PTCK
PTMS
STMS1
STMS1
PTMS
Z
STDI0
Z
CTDI
Z
L H H L H H
H
–
H
PTCK
CTDI
Z
Z
L H H L H L
H
–
H
PTCK
PTMS
STDI0
STDI1
STDI1
Z
CTDI
Z
L H H L L H
H
–
H
PTCK
PTMS
CTDI
Z
Z
L H H L L L
H
–
H
PTCK
PTMS
PTMS
STDI0
CTDI
Z
H X X X X X
L
–
L
PTCK
H
H
H
Z
Z
Z
Z
H
H X X X X X
H
RESET
H
PTCK
H
H
H
Z
Z
Z
Z
CTDI
H X X X X X
H
MATCH
H
PTCK
See Function Table 3
STMS0
STMS0
STMS0
H X X X X X
H
NO MATCH
HARD ERROR
§
H
PTCK
STMS2
STMS2
STMS2
STMS1
STMS1
STMS1
Z
Z
Z
Z
CTDI
H X X X X X
H
H
PTCK
Z
Z
Z
Z
CTDI
H X X X X X
H
DISCONNECT
H
PTCK
Z
Z
Z
Z
CTDI
H X X X X X
H
TEST
SYNCHRONIZATION
H
PTCK
PTMS
PTMS
PTMS
PTDI
PTDI
PTDI
Z
CTDI
In normal operation of IEEE Std 1149.1-compliant architectures, it is recommended that TMS be high prior to release of TRST. The BYP/TRST
connect status ensures that this condition is met at STMS, regardless of the applied PTMS. Also, it is recommended that STMS be kept high
for a minimum duration of five PTCK cycles following assertion of PTRST, either by maintaining PTRST low or by setting PTMS high. This ensures
that devices with and without TRST inputs are moved to their Test-Logic-Reset TAP states. It is expected that, in normal application, this condition
occurs only when BYP5 is fixed at the low state. In such a case, upon release of PTRST, the LASP immediately resumes the BYP connect status.
STMS level before steady-state conditions were established
§
The linking shadow protocol is well defined. Some variations in the protocol are tolerated (see protocol errors). Those that are not tolerated
produce the result HARD ERROR and cause disconnect, as indicated.
PTDI and PTMS are connected to STDO and STMS, respectively, only on those secondary TAPs whose TAP state is Pause-DR or Pause-IR
while PTDO is high impedance. The result of linking shadow protocol on a secondary TAP whose state is Test-Logic-Reset or Run-Test-Idle is
DISCONNECT.
相關(guān)PDF資料
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