參數(shù)資料
型號(hào)： SNJ54LVT8986HV
廠商： Texas Instruments, Inc.
英文描述： 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
中文描述： 3.3 V的連接尋址掃描港口多點(diǎn)尋址IEEE標(biāo)準(zhǔn)1149.1（JTAG接口）技術(shù)咨詢收發(fā)器
文件頁(yè)數(shù)： 22/51頁(yè)
文件大?。?/td> 880K
代理商： SNJ54LVT8986HV
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reset address
The reset address (RSA) is one of the three internally dedicated addresses that are recognized globally. When
an LASP receives the RSA, it immediately responds by assuming the RESET status in which PTDO and
STDO
2
–
STDO
0
are at high impedance and STMS
2
–
STMS
0
are forced to the high level. This has the effect of
deselecting and resetting to Test-Logic-Reset state the scan chain associated with the LASP secondary TAP.
No acknowledge protocol is sent. Figures 15 and 16 show the linking shadow protocol timing for RESET result
when the prior LASP connect status is ON and OFF, respectively.
test synchronization address
The test synchronization address (TSA) is one of the three internally dedicated addresses that are recognized
globally. When an LASP receives the TSA, it immediately responds by assuming the MULTICAST status, in
which PTDI and PTMS are connected to STDO and STMS, respectively, of only those secondary TAPs whose
TAP state is Pause-DR or Pause-IR while PTDO is high impedance. No acknowledge protocol is sent. The result
of receipt of TSA on a secondary TAP whose TAP state is Test-Logic-Reset or Run-Test-Idle is disconnect.
Figures 17 and 18 show the linking shadow protocol timing for TEST SYNCHRONIZATION result when the prior
LASP connect status is ON and OFF, respectively. The TSA allows simultaneous operation of the scan chains
of all selected LASPs, either for global TAP-state movement or for scan input of common serial test data via
PTDI. This is especially useful in the former case, to simultaneously move such scan chains into the
Run-Test/Idle state in which module-level or module-to-module BIST operations can operate synchronous to
TCK in that TAP state and, in the later case, to scan common test setup/data into multiple like modules. In
conjunction with the use of the pass-through input/output pairs (PX to SX
2
–
SX
0
and PY to SY
2
–
SY
0
), the
multicast mode can be effective for ISP of like modules.
protocol bypass
Protocol bypass is selected by a low BYP
5
input. This protocol-bypass mode forces the LASP into BYP status.
The remaining bypass BYP
4
–
BYP
0
inputs are used for configuring the primary-to-secondary TAP connections,
regardless of previous linking shadow protocol results, and the corresponding CON
2
–
CON
0
outputs are made
active (low). Receipt of the linking shadow protocols is disabled. When BYP
5
is taken low, the
primary-to-secondary TAP connections are configured immediately (asynchronously to PTCK). The PTMS
signal also is connected to its respective secondary TAP signal STMS
2
–
STMS
0
unless PTRST is low, in which
case STMS
2
–
STMS
0
remain high until PTRST is released. Also, the linking-shadow protocol receive block is
reset to its power-up state and is held in this state, such that select protocols appearing at the primary TAP are
ignored. When the BYP
5
input is released (taken high), the LASP immediately (asynchronously to PTCK)
resumes the connect status selected by the last valid linking shadow protocol. The linking shadow protocol
receive block again is enabled to respond to select protocols. Figures 19 and 20 show protocol-bypass timing
when the LASP connect status before BYP
5
active is ON and OFF, respectively.
asynchronous reset
While the PTRST input always is buffered directly to the STRST
2
–
STRST
0
outputs, it also serves as an
asynchronous reset for the LASP. Given that BYP
5
is high, when PTRST goes low, the LASP immediately
assumes TRST status, in which CON
2
–
CON
0
are high and PTDO and STDO
2
–
STDO
0
are at high impedance.
Otherwise, if BYP
5
is low, the LASP assumes BYP/TRST status. In either case, STMS
2
–
STMS
0
are set high
so that connected IEEE Std 1149.1-compliant devices can be driven synchronously to their Test-Logic-Reset
states. While PTRST is low, receipt of linking shadow protocols is disabled. Figures 21 and 22 show
asynchronous reset timing when the LASPs connect status before PTRST active is ON and OFF, respectively.
Figure 23 shows asynchronous reset timing when BYP
5
is low.
connect indicators
The CON
2
–
CON
0
outputs indicate secondary-scan-port activity (STDO
2
–
STDO
0
, STMS
2
–
STMS
0
active),
regardless of whether such activity is achieved via protocol bypass or linking shadow protocol. When
acknowledge protocol is in progress, the CON
2
–
CON
0
outputs are high.
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