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參數(shù)資料
| 型號： | SNJ54LVT8986HV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS |
| 中文描述： | 3.3 V的連接尋址掃描港口多點(diǎn)尋址IEEE標(biāo)準(zhǔn)1149.1（JTAG接口）技術(shù)咨詢收發(fā)器 |
| 文件頁數(shù)： | 17/51頁 |
| 文件大?。?/td> | 880K |
| 代理商： | SNJ54LVT8986HV |
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SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
protocol errors
Protocol errors occur when bit pairs are received out of sequence. Some of these sequencing errors can be
tolerated and produce protocol result SOFT ERROR, and no specific action occurs as a result. Other errors
represent cases where the message information could be incorrectly received and produce protocol result
HARD ERROR, and these are characterized by sequences in which at least one bit of message data has been
properly transmitted, followed by a sequencing error; when protocol result HARD ERROR occurs, any
connection to an LASP is dissolved. Table 1 lists the bit-pair sequences that produce protocol results
SOFT ERROR and HARD ERROR. A HARD ERROR also results when the primary TAP state changes during
select protocol, following the proper transmission of at least one bit of address data. Figures 5, 6, and 7 show
shadow-protocol timing in case of protocol result HARD ERROR, while Figure 8 shows shadow-protocol timing
in the case of protocol result SOFT ERROR.
Table 1. Linking Shadow Protocol Errors
SOFT ERROR
HARD ERROR
I(D)I
I(D)(S)I
I(D)(S)(D)I
IS(D)I
I(S)I
IS(D)S(D)I
IS(S)(D)I
IS(D)S(S)I
IS(S)(D)(S)I
A bit-pair token in parentheses represents
one or more instances.
long address
Receipt of an address longer than 10 bits produces protocol result HARD ERROR, and the LASP assumes
OFF status. The sole exceptions are when all data 1s are received or all data 0s are received. In these special
cases, the global addresses represented by these bit sequences are observed and appropriate action taken.
That is, in the case that only data 1s (ten or more) are received, the shadow-protocol result is TEST
SYNCHRONIZATION (if the primary TAP state is Pause-DR or Pause-IR) and, in the case that only data 0s (ten
or more) are received, the linking shadow-protocol result is RESET (see test-synchronization address and reset
address).
short address
In all cases, receipt of an address of less than ten bits produces protocol result HARD ERROR, and the LASP
assumes OFF status.
long/short command
In all cases, receipt of a command that is not a multiple of six bits produces protocol result HARD ERROR, and
the LASP assumes OFF status.
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PDF描述 |
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| SNJ54LVTH241W | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54LVTH241 | Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000 |
| SN54LVTH241FK | Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000 |
| SN54LVTH241J | Octal 3-State Non-Inverting Transparent Latch; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000 |
| SNJ54LVTH241FK | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
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