參數(shù)資料
型號(hào)： SNJ54LVT8986HV
廠商： Texas Instruments, Inc.
英文描述： 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
中文描述： 3.3 V的連接尋址掃描港口多點(diǎn)尋址IEEE標(biāo)準(zhǔn)1149.1（JTAG接口）技術(shù)咨詢收發(fā)器
文件頁(yè)數(shù)： 18/51頁(yè)
文件大?。?/td> 880K
代理商： SNJ54LVT8986HV
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
architecture
Blocks for linking shadow protocol receive and linking shadow protocol transmit are responsible for receipt of
select protocol and transmission of acknowledge protocol, respectively. Connect control block monitors the
primary TAP state to enable receipt/acknowledge of shadow protocols in appropriate states (namely, the stable,
non-shift TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR). Upon receipt of a valid
shadow protocol, this block performs the address and position matching required to compute the
shadow-protocol result.
Based on the linking shadow protocol result or protocol bypass (BYP
4
–
BYP
0
) inputs, the connect control block
configures the secondary TAP network. In conjunction, it also sets the states of and CON
2
–
CON
0
outputs.
TAP-state monitor
The TAP-state monitor is a synchronous finite-state machine that monitors the primary TAP state. The state
diagram is shown in Figure 4 and mirrors that specified by IEEE Std 1149.1. The TAP-state monitor proceeds
through its states based on the level of PTMS at the rising edge of PTCK. Each state is described both in terms
of its significance for LASP devices and for connected IEEE Std 1149.1-compliant devices (called targets).
However, the monitor state (primary TAP) can be different from that of disconnected scan chains (secondary
TAP).
Test-Logic-Reset
The LASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the LASP can be forced
asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the LASP is
enabled to receive and respond to linking shadow protocols. The LASP does not recognize the TSA in this state.
For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal
logic function of the device is performed. The instruction register is reset to an opcode that selects the optional
IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their
power-up values.
Run-Test/Idle
In the stable Run-Test/Idle state, the LASP is enabled to receive and respond to linking shadow protocols. The
LASP does not recognize the TSA in this state. For a target device, Run-Test/Idle is a stable state in which the
test logic actively can be running a test or can be idle.
相關(guān)PDF資料
PDF描述
SNJ54LVTH241W 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVTH241 Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000
SN54LVTH241FK Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000
SN54LVTH241J Octal 3-State Non-Inverting Transparent Latch; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000
SNJ54LVTH241FK 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
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