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| 型號(hào)： | SNJ54LVT8986HV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS |
| 中文描述： | 3.3 V的連接尋址掃描港口多點(diǎn)尋址IEEE標(biāo)準(zhǔn)1149.1（JTAG接口）技術(shù)咨詢收發(fā)器 |
| 文件頁數(shù)： | 15/51頁 |
| 文件大小： | 880K |
| 代理商： | SNJ54LVT8986HV |
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SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
application information (continued)
Additionally, in Pause-DR and Pause-IR TAP states, a third global address [test-synchronization address (TSA)]
can be invoked to allow simultaneous TAP-state changes and multicast scan-in operations to selected modules.
In this case, PTDO is at high impedance. This is especially useful in the former case, for allowing selected
modules to be moved simultaneously to the Run-Test-Idle TAP state for module-level or module-to-module
built-in self-test (BIST) functions, which operate synchronously to TCK in that TAP state and, in the latter case,
for scanning common test setup/data into multiple like modules. In conjunction with the use of the pass-through
input/output pairs (PX to SX
2
–
SX
0
and PY to SY
2
–
SY
0
), the multicast mode can be effective for ISP of like
modules.
addressing the LASP
Addressing of an LASP in a system is accomplished by linking shadow protocols, which are received at PTDI
synchronously to PTCK. These protocols can occur only in the following stable TAP states: Test-Logic-Reset,
Run-Test/Idle, Pause-DR, and Pause-IR. Linking shadow protocols never occur in Shift-DR or Shift-IR states
to prevent contention on the signal bus to which PTDO is wired. Additionally, the LASP PTMS must be held at
a constant low or high level throughout a linking shadow protocol. If TAP-state changes occur in the midst of
a protocol, the protocol is aborted and the select-protocol state machine returns to its initial state.
These protocols are based on a serial bit-pair signaling scheme used by the ASP (8996), in which two bit-pair
combinations (data one, data zero) are used to represent data and the other two bit-pair combinations (select,
idle) are used for framing
—
that is, to indicate where data begins and ends. This allows the LASP to coexist and
be fully compatible with the ASP.
These bit pairs are received serially at PTDI (or transmitted serially at PTDO) synchronously to PTCK as follows
and as illustrated in Figure 2:
1.
The idle bit pair (I) is represented as two consecutive high signals.
2.
The select bit pair (S) is represented as two consecutive low signals.
3.
The data-one bit pair (D) is represented as a low signal, followed by a high signal.
4.
The data-zero bit pair (D) is represented as a high signal, followed by a low signal.
PTCK
PTDI
or
PTDO
First Bit of Pair Is Transmitted
First Bit of Pair Is Received
Second Bit of Pair Is Transmitted
Second Bit of Pair Is Received
Figure 2. Bit-Pair Timing (Data Zero Shown)
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