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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 8/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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PC Card Controller Programming Model
89
September 2005
SCPS110
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. Some of the bits are
global in nature and must be accessed only through function 0. See Table 48 for a complete description of
the register contents.
PCI register offset:
80h (Function 0)
Register type:
Read-only, Read/Write
Default value:
0844 9060h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
1
0
1
0
1
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
1
0
1
0
1
0
Table 48. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
3130 §
SER_STEP
RW
Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI
interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI
interrupt slots.
00 = INTA/INTB/INTC/INTD signal in INTA/INTB/INTC/INTD slots (default)
01 = INTA/INTB/INTC/INTD signal in INTB/INTC/INTD/INTA slots
10 = INTA/INTB/INTC/INTD signal in INTC/INTD/INTA/INTB slots
11 = INTA/INTB/INTC/INTD signal in INTD/INTA/INTB/INTC slots
29 §
INTRTIE
RW
This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset
3Dh, see Section 4.24). This bit has no effect on INTC or INTD.
28
TIEALL
RW
This bit ties INTA, INTB, INTC, and INTD internally (to INTA), and reports this through the interrupt pin
register (PCI offset 3Dh, see Section 4.24).
27
PSCCLK
RW
P2C power switch clock. The PCIxx12 CLOCK signal clocks the serial interface power switch and the
internal state machine. The default state for this bit is 0b, requiring an external clock source provided to
the CLOCK terminal. Bit 27 can be set to 1b, allowing the internal oscillator to provide the clock signal.
0 = CLOCK is provided externally, input to the controller
1 = CLOCK is generated by the internal oscillator and driven by the controller (default)
26 §
SMIROUTE
RW
SMI interrupt routing. This bit selects whether IRQ2 or CSC is signaled when a write occurs to power a
PC Card socket.
0 = PC Card power change interrupts are routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes
25
SMISTATUS
RW
SMI interrupt status. This bit is set when a write occurs to set the socket power, and the SMIENB bit is set.
Writing a 1b to this bit clears the status.
0 = SMI interrupt is signaled
1 = SMI interrupt is not signaled
24 §
SMIENB
RW
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit defaults to 0b (disabled).
0 = SMI interrupt mode is disabled (default)
1 = SMI interrupt mode is enabled
23
RSVD
R
Reserved
22
CBRSVD
RW
CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven low
when a CardBus card has been inserted. When this bit is low, these signals are placed in a high-impedance
state.
0 = Place the CardBus RSVD terminals in a high-impedance state
1 = Drive the CardBus RSVD terminals low (default)
21
VCCPROT
RW
VCC protection enable.
0 = VCC protection is enabled for 16-bit cards (default)
1 = VCC protection is disabled for 16-bit cards
These bits are cleared only by the assertion of GRST.
§ These bits are global in nature and must be accessed only through function 0.
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