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參數(shù)資料
| 型號(hào)： | SNA7412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 213/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SNA7412ZHK |
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Introduction
30
September 2005
SCPS110
Table 27. Serial PC Card Power Switch Terminals
Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power
switch terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
EXTERNAL
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
EXTERNAL
COMPONENTS
CLOCK
A09
Power switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27
(P2CCLK) in the system control register (offset 80h, see Section 4.29).
I/O
TTLI1
TTLO1
PCMCIA power
switch
DATA
B09
Power switch data. DATA is used to communicate socket power control information
serially to the power switch.
O
LVCO1
PCMCIA power
switch
LATCH
C09
Power switch latch. LATCH is asserted by the controller to indicate to the power
switch that the data on the DATA line is valid.
O
LVCO1
PCMCIA power
switch
Table 28. Parallel PC Card Power Switch Terminals
Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power
switch terminals.
TERMINAL
I/O
DESCRIPTION
INPUT
OUTPUT
NAME
NO.
I/O
DESCRIPTION
INPUT
OUTPUT
VD1/VCCD0
VD0/VCCD1
A09
C04
I/O
Logic controls to the TPS2211A PC Card power interface switch to control VCCCB.
RSVD/VD0/VCCD1 (terminal C04) controls the power switch interface mode. If it is
pulled up, the power switch interface uses the 3-pin serial power interface. If it is
pulled down, the power switch interface uses the 4-pin parallel power switch
interface.
TTLI1
LVCI1
TTLO1
LVCO1
VD3/VPPD0
VD2/VPPD1
C09
B09
O
Logic controls to the TPS2211A PC Card power interface switch to control VPP
LVCO1
Table 29. PCI System Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.
TERMINAL
DESCRIPTION
I/O
INPUT
POWER
EXTERNAL
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
POWER
RAIL
EXTERNAL
COMPONENTS
GRST
K05
Global reset. When the global reset is asserted, the GRST signal causes the
controller to place all output buffers in a high-impedance state and reset all internal
registers. When GRST is asserted, the controller is completely in its default state. For
systems that require wake-up from D3, GRST is normally asserted only during initial
boot. PRST must be asserted following initial boot so that PME context is retained
when transitioning from D3 to D0. For systems that do not require wake-up from D3,
GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is
protected from the GRST, and the internal registers are preserved. All outputs are
placed in a high-impedance state, but the contents of the registers are preserved.
I
LVCI2
Power-on reset or
tied to PRST
PCLK
L01
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI
signals are sampled at the rising edge of PCLK.
I
PCII3
VCCP
PRST
K03
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to
place all output buffers in a high-impedance state and reset some internal registers.
When PRST is asserted, the controller is completely nonfunctional. After PRST is
deasserted, the controller is in a default state.
When SUSPEND and PRST are asserted, the controller is protected from PRST
clearing the internal registers. All outputs are placed in a high-impedance state, but
the contents of the registers are preserved.
I
PCII3
VCCP
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