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參數(shù)資料
| 型號： | SMC9-65608EV-45SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | Static RAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 45 ns, DIP32 |
| 封裝： | 0.400 INCH, SIDE BRAZED, DIP-32 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 159K |
| 代理商： | SMC9-65608EV-45SB |
M65608E
Rev. E – June 5, 2000
8
Write Cycle 3. CS1 or CS2 Controlled.
Note :
12. The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be
actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be
referenced to the actived edge of the signal that terminates the write.
Data out is high impedance if OE = VIH.
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