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參數(shù)資料
| 型號： | SMC9-65608EV-45SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | Static RAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 45 ns, DIP32 |
| 封裝： | 0.400 INCH, SIDE BRAZED, DIP-32 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 159K |
| 代理商： | SMC9-65608EV-45SB |
M65608E
Rev. E – June 5, 2000
4
Consumption
SYMBOL
DESCRIPTION
65608
– 30
65608
– 45
UNIT
VALUE
ICCSB (5)
Standby supply current
2
mA
max
ICCSB1 (6)
Standby supply current
300
A
max
ICCOP (7)
Dynamic operating current
130
100
mA
max
Notes :
5. CS1 ≥ VIH or CS2 ≤ VIL and CS1 ≤ VIL.
6. CS1 ≥ Vcc – 0.3 V or, CS2 < Gnd + 0.3 V and CS1 ≤ 0.2 V
7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
AC Parameters
Input pulse levels :
Gnd to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input rise :
5 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input timing reference levels :
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output loading IOL/IOH (see figure 1a and 1b) :
+ 30 pF
. . . . . . . . .
AC Test Loads Waveforms
Figure 1a
Figure 1b
Figure 2
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup
in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1.
During data retention chip select CS1 must be held
.
high within VCC to VCC -0.2 V or, chip select CS2
must be held low within GND to GND + 0.2 V.
2.
Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power
dissipation.
3.
During power up and power down transitions CS1
and OE must be kept between VCC + 0.3 V and
70 % of VCC, or with CS2 between GND and GND
- 0.3 V.
4. The RAM can begin operation > TR ns after Vcc
reaches the minimum operation voltages (4.5 V).
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