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參數(shù)資料
| 型號： | SMC9-65608EV-45SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | Static RAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 45 ns, DIP32 |
| 封裝： | 0.400 INCH, SIDE BRAZED, DIP-32 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 159K |
| 代理商： | SMC9-65608EV-45SB |
M65608E
Rev. E – June 5, 2000
6
Write Cycle
SYMBOL
PARAMETER
65608
– 30
65608
– 45
UNIT
VALUE
TAVAW
Write cycle time
30
45
ns
min
TAVWL
Address set-up time
0
ns
min
TAVWH
Address valid to end of write
22
35
ns
min
TDVWH
Data set-up time
18
25
ns
min
TE1LWH
CS1 low to write end
22
35
ns
min
TE2HWH
CS2 high to write end
22
35
ns
min
TWLQZ
Write low to high Z (11)
8
15
ns
max
TWLWH
Write pulse width
22
35
ns
min
TWHAX
Address hold from to end of write
0
ns
min
TWHDX
Data hold time
0
ns
min
TWHQX
Write high to low Z (11)
0
ns
min
Read Cycle
SYMBOL
PARAMETER
65608
– 30
65608
– 45
UNIT
VALUE
TAVAV
Read cycle time
30
45
ns
min
TAVQV
Address access time
30
45
ns
max
TAVQX
Address valid to low Z
5
ns
min
TE1LQV
Chip-select1 access time
30
45
ns
max
TE1LQX
CS1 low to low Z (11)
3
ns
min
TE1HQZ
CS1 high to high Z (11)
18
20
ns
max
TE2HQV
Chip-select2 access time
30
45
ns
max
TE2HQX
CS2 high to low Z (11)
3
ns
min
TE2LQZ
CS2 low to high Z (11)
18
20
ns
max
TGLQV
Output Enable access time
12
15
ns
max
TGLQX
OE low to low Z (11)
0
ns
min
TGHQZ
OE high to high Z (11)
8
15
ns
max
Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.).
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