參數(shù)資料
型號: SK100EL33WD
元件分類: 諧振器
英文描述: 100EL SERIES, PRESCALER, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 4/5頁
文件大?。?/td> 380K
代理商: SK100EL33WD
4
www.semtech.com
TEST AND MEASUREMENT PRODUCTS
SK100EL33W
Revision 3 / January 24, 2003
Notes:
1.
100K circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
2.
Minimum input swing for which AC parameters are guaranteed.
3.
CMR range is referenced to the most positive side of the differential input signal. Normal operation
is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.7V.
4.
Voltages referenced to VCC = 0V.
5. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
6. For part ordering description, see TMD Part Ordering Information Data Sheet.
AC Characteristics
AC Characteristics (continued)
AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices
AN1005 - Using ECL / LVECL Devices as PECL / LVPECL
AN1006 - Designing with 10K and 100K ECL / PECL Devices
Application Notes
相關(guān)PDF資料
PDF描述
SK100EL34WD 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SK100EL39WDT 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
SK100EL52WU 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC
SK100EL52WDT 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
SK100EL56WDT 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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