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參數(shù)資料
| 型號： | SK100EL39WDT |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 331K |
| 代理商： | SK100EL39WDT |
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 2 / January 28, 2003
PRELIMINARY
SK100EL39W
÷2/4, ÷4/6 Clock
Generation Chip
Description
Features
The SK100EL39W is a low skew, ÷2/4, ÷4/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or,
if positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device.
If a single-ended input is to be used, the VBB output
should be connected to the CLK* input and bypassed
to VCC via a 0.01 F capacitor. The VBB output is
designed to act as the switching reference of the input
of the EL39W under single-ended input conditions. As
a result, this pin can only source/sink up to 0.5 mA of
current.
The common enable (EN*) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the
falling edge of the input clock, therefore, all associated
specification limits are referenced to the negative edge of
the clock input.
Upon start-up, the internal flip-flops will attain a random
state; therefore, for systems which utilize multiple EL39Ws,
the master reset (MR) input must be asserted to ensure
synchronization. For systems which only use one EL39W,
the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2/4 and
the ÷4/6 outputs of a single device.
Extended Supply Voltage Range: (VEE = 5.5V to
3.0V, VCC = 0V) or (VCC = +3.0V to +5.5V,
VEE = 0V)
50 ps Output-to-Output Skew
VBB Output
Synchronous Enable/Disable
Master Reset for Synchronization
Internal 75K Input Pull-Down Resistors
Fully Compatible with MC100EL39 and
MC100LVEL39
Specified Over Industrial Temperature Range:
40oC to 85oC
ESD Protection of >4000V
Available in 20 Lead SOIC Package
÷ 2/4
R
÷ 4/6
R
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
DIVSELa
CLK
CLK*
EN*
MR
DIVSELb
Functional Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| SK100EL52WDT | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK100EL56WDT | 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| SK100EL57WU | 100E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, UUC |
| SK100EL58WD | 100EL SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SK100ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100EP111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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