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參數(shù)資料
| 型號： | SK100EL39WDT |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大?。?/td> | 331K |
| 代理商： | SK100EL39WDT |
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www.semtech.com
TEST AND MEASUREMENT PRODUCTS
Revision 2 / January 28, 2003
PRELIMINARY
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Semtech Corporation
Test and Measurement Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858) 695-1808 FAX: (858) 695-2633
Contact Information
Ordering Information
Notes:
1. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.
2. Minimum input swing for which AC parameters guaranteed.
3. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.2V.
4. Voltages referenced to VCC = 0V, ECL configuration.
5. The within device skew is defined as the worst case difference between any two similar delay paths
within a single device.
6. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
7. For part ordering description, see TMD Part Ordering Information Data Sheet.
AC Characteristics (continued)
AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL - to - TTL / LVTTL / CMOS / LVCMOS
AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices
AN1005 - Using ECL / LVECL Devices as PECL / LVPECL
AN1006 - Designing with 10K and 100K ECL / PECL Devices
Application Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| SK100EL52WDT | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK100EL56WDT | 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| SK100EL57WU | 100E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, UUC |
| SK100EL58WD | 100EL SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100EP111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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