參數(shù)資料
型號: SK100EL56WDT
元件分類: 編、解碼器及復用、解復用
英文描述: 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20
封裝: SOIC-20
文件頁數(shù): 1/4頁
文件大?。?/td> 85K
代理商: SK100EL56WDT
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 2/ September 4, 2002
SK100EL56W
Dual 2:1
Differential Multiplexer
Description
Features
Functional Block Diagram
Pin Names
The SK100EL56W is a Dual 2:1 Differential Multiplexer.
It is fully differential and compatible with MC100EL56
and MC100LVEL56.
This device features both
individual and common select inputs to address both
data path and random logic applications.
Multiple VBB outputs are provided for single-ended use or
DC bias for AC coupling to the device. VBB is an output
pin and should be used as a bias for the SK100EL56W
as its current source/sink capability is limited.
Whenever used, the VBB output pins should be
bypassed to VCC via 0.01 F capacitors. When both
differential inputs are left open, the D input will pull
down to VEE, and the D* input will bias at VCC/2,
forcing the Q output low.
Extended Supply Voltage Range (VEE = –5.5V to
–3.0V, VCC = 0V) or VCC = +3.0V to 5.5V, VEE =
0V)
High Bandwidth Output Transition
500 ps Propagation Delay (typical)
VBB Output
Internal Input Pulldown Resistors
New Differential Input Common Mode Range
Fully Compatible with MC100EL56 and
MC100LVEL56
ESD Protection of >4000V
Industrial Temperature Range:
–40oC to +85oC
Available in 20 Pin SOIC Package
D0a
D0b
D0a*
D0b*
D1a
D1a*
D1b
D1b*
VBB0
VBB1
VCC
Q0
COM_SEL
SEL1
Q1
Q1*
VEE
Q0*
SEL0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
n
i
Pn
o
i
t
c
n
u
F
,
*
a
0
D
,
a
0
D
*
b
0
D
,
b
0
D
s
t
u
p
n
I
a
t
a
D
l
a
i
t
n
e
r
e
f
i
D
1
L
E
S
,
0
L
E
Ss
t
u
p
n
I
t
c
e
l
e
S
l
a
u
d
i
v
i
d
n
I
L
E
S
_
M
O
Cs
t
u
p
n
I
t
c
e
l
e
S
n
o
m
o
C
1
Q
,
0
Qs
t
u
p
t
u
O
e
u
r
T
*
1
Q
,
*
0
Q
s
t
u
p
t
u
O
d
e
t
r
e
v
n
I
V
,
0
B
V
1
B
s
e
g
a
t
l
o
V
e
c
n
e
r
e
f
e
R
t
u
p
t
u
O
T
C
E
L
E
SA
T
A
D
HA
LB
Function Table
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