參數(shù)資料
型號(hào): SK100EL52WDT
元件分類: 鎖存器
英文描述: 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
封裝: SOIC-8
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 374K
代理商: SK100EL52WDT
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 2 / January 27, 2003
SK100EL52W
Differential Data and
Clock D Flip-Flop
Description
Features
Functional Block Diagram
PIN Description
The SK100EL52W is a differential data, differential clock
D flip-flop. This device is fully compatible with
MC100EL52 and functionally equivalent to the E452
devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E452, the EL52W is ideally
suited for those applications which require the ultimate
in AC performance.
Data enters the master portion of the flip-flop when the
clock is LOW and is transferred to the slave, and thus the
outputs, upon a positive transition of the clock. The
differential clock inputs also allow the EL52W to be used
as a negative edge triggered device.
The EL52W employs input clamping circuitry so that, under
open input conditions (pulled down to VEE), the outputs
of the device will remain stable.
Extended Supply Voltage Range: (VEE = 3.0V
to 5.5V, VCC = 0V) or (VCC = +3.0V to +5.5V,
VEE = 0V)
365 ps Propagation Delay
2.0 GHz Toggle Frequency
Internal 75K Input Pull-Down Resistors
Fully Compatible with MC10EL52 and
MC100EL52
Specified Over Industrial Temperature Range:
40oC to +85oC
ESD Protection of >4000V
Available in 8-Pin SOIC Package
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it
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F
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D
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Dt
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a
t
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D
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K
L
C
,
K
L
Ct
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l
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Q
,
Qt
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p
t
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O
a
t
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D
DK
L
CQ
LZ
L
HZ
H
NOTE: Z = Low-to-High transition.
Truth Table
1
2
3
4
5
6
7
8
Flip-Flop
D
D*
CLK
CLK*
VEE
VCC
Q
Q*
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