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參數(shù)資料
| 型號(hào)： | SK100EL33WD |
| 元件分類(lèi)： | 諧振器 |
| 英文描述： | 100EL SERIES, PRESCALER, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 380K |
| 代理商： | SK100EL33WD |
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 3 / January 24, 2003
SK100EL33W
÷4 Divider
Description
Features
Functional Block Diagram
The SK100EL33W is a ÷4 Divider. This device is fully
compatible with MC100EL33 and MC100LVEL33.
The SK100EL33W provides a VBB output for either
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for
the SK100EL33W as its current sink/source capability
is limited. Whenever used, the VBB pin should be
bypassed to VCC via a 0.01 F capacitor.
The Reset pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state. The Reset pin allows for the
synchronization of multiple EL33Ws in a system.
Extended Supply Voltage Range: (VEE = 5.5V to
3.0V, VCC = 0V) or (VCC = +3.0V to +5.5V, VEE = 0V)
High Bandwidth Output Transition
560 ps (Typ.) Propagation Delay
VBB Output
75K Internal Input Pulldown Resistor
4.0 GHz Toggle Frequency
New Differential Input Common Mode Range
Fully Compatible with MC100EL33 and
MC100LVEL33
ESD Protection of >4000V
Industrial Temperature Range: 40oC to 85oC
Available in 8-Pin SOIC (150 mils) Package
Flammability Rate: UL-94 code V-0
Moisture sensitivity: Level 1
Pin Description
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F
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C
,
K
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C
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Q
,
Q
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R
V B
B
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1
2
3
4
8
7
6
5
Reset
CLK
CLK*
VCC
VEE
VBB
Q
Q*
÷ 4
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SK100EL34WD | 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SK100EL39WDT | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| SK100EL52WDT | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK100EL56WDT | 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100EL34WD | 制造商:Semtech Corporation 功能描述:Clock Divider 16-Pin SOIC |
| SK100ELT21W | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱(chēng):Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
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