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| 型號： | SIO10N268 |
| 廠商： | SMSC Corporation |
| 英文描述： | Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports |
| 中文描述： | Advenced筆記本電腦的I / O ISA或設(shè)計(jì)的X LPC總線接口的I / O，內(nèi)存，和FWH仿真和四Srial港口 |
| 文件頁數(shù)： | 9/251頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | SIO10N268 |
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Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 9
Rev. 0.5 (03-24-05)
DATASHEET
13.1
13.2
13.3
13.4
Chapter 14
14.1
Chapter 15
Entering and Exiting Test Mode...................................................................................................247
Pin List of XNOR Chain ...............................................................................................................248
Setup of XNOR Chain..................................................................................................................248
Testing Procedure........................................................................................................................249
Package Outline ............................................................................................................251
128 Pin TQFP Package Outline, 14x14x1.0 Body, 2 MM Footprint ............................................251
References......................................................................................................................253
LIST OF FIGURES
Figure 5.1 - SIO10N268 Block Diagram.......................................................................................................................29
Figure 8.1 - FWH Memory Cycle Preamble..................................................................................................................43
Figure 8.2 - Single Byte Read......................................................................................................................................43
Figure 8.3 - Single Byte Write ......................................................................................................................................44
Figure 8.4 - X-Bus Interface, Mode 1 ...........................................................................................................................48
Figure 8.5 - X-Bus Interface, Mode 2 ...........................................................................................................................48
Figure 8.6 - X-Bus Interface, Mode 3 ...........................................................................................................................49
Figure 8.7 - Serial Data................................................................................................................................................95
Figure 8.8 - Infrared Interface Block Diagram ............................................................................................................110
Figure 8.9 - CLKRUN# System Implementation Example..........................................................................................144
Figure 8.10 - Clock Start Illustration...........................................................................................................................145
Figure 8.11 - GPIO Function......................................................................................................................................149
Figure 12.1 - Power-Up Timing ..................................................................................................................................222
Figure 12.2 – 14MHZ Clock Timing............................................................................................................................223
Figure 12.3 – PCI Clock Timing .................................................................................................................................223
Figure 12.4 - Reset Timing.........................................................................................................................................224
Figure 12.5 - Output Timing Measurement Conditions, LPC Signals.........................................................................224
Figure 12.6 – Input Timing Measurement Conditions, LPC Signals...........................................................................224
Figure 12.7 - I/O Write................................................................................................................................................225
Figure 12.8 - I/O Read ...............................................................................................................................................225
Figure 12.9 - DMA Request Assertion Through LDRQ#.............................................................................................225
Figure 12.10 – DMA Write (First Byte) .......................................................................................................................225
Figure 12.11 - DMA Read (First Byte)........................................................................................................................226
Figure 12.12 – X-Bus I/O Read Timing ......................................................................................................................226
Figure 12.13 - X-Bus Write Timing.............................................................................................................................227
Figure 12.14 – X-Bus and LPC I/O Read Cyle...........................................................................................................228
Figure 12.15 – X-Bus and LPC I/O Write Cycle .........................................................................................................229
Figure 12.16 - X-Bus Memory Read...........................................................................................................................230
Figure 12.17
X-Bus Memory Write..........................................................................................................................231
Figure 12.18 - Microprocessor Write Timing ..............................................................................................................232
Figure 12.19 - DMA Timing........................................................................................................................................233
Figure 12.20 – Floppy Disk Drive Timing (AT Mode Only).........................................................................................234
Figure 12.21 - EPP 1.9 Data or Address Write Cycle.................................................................................................235
Figure 12.22 - EPP 1.9 Data or Address Read Cycle.................................................................................................236
Figure 12.23 - EPP 1.7 Data or Address Write Cycle.................................................................................................237
Figure 12.24 - EPP 1.7 Data or Address Read Cycle.................................................................................................237
Figure 12.25 - Parallel Port FIFO Timing ...................................................................................................................239
Figure 12.26 - ECP Parallel Port Forward Timing ......................................................................................................240
Figure 12.27 - ECP Parallel Port Reverse Timing......................................................................................................241
Figure 12.28 - IrDA Receive Timing...........................................................................................................................242
Figure 12.29 - IrDA Transmit Timing..........................................................................................................................243
Figure 12.30 - Amplitude Shift Keyed IR Receive Timing...........................................................................................244
Figure 12.31 - Amplitude Shift Keyed IR Transmit Timing..........................................................................................245
Figure 12.32 - Setup and Hold Time ..........................................................................................................................245
Figure 12.33 - Serial Port Data...................................................................................................................................246
Figure 13.1 – XNOR-Chain Test Structure.................................................................................................................247
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