
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 8
SMSC SIO10N268
DATASHEET
10.4.58
10.4.59
10.4.60
10.4.61
10.4.62
10.4.63
10.4.64
10.4.65
10.4.66
10.4.67
10.4.68
10.4.69
10.4.70
10.4.71
10.4.72
10.4.73
10.4.74
10.4.75
10.4.76
10.4.77
10.4.78
10.4.79
CR3A ................................................................................................................................................199
CR3B – CR3F...................................................................................................................................199
CR40.................................................................................................................................................200
CR41.................................................................................................................................................200
CR42.................................................................................................................................................201
CR43.................................................................................................................................................201
CR44.................................................................................................................................................202
CR45.................................................................................................................................................203
CR46.................................................................................................................................................204
CR48.................................................................................................................................................205
CR49.................................................................................................................................................205
CR4A.................................................................................................................................................206
CR4B.................................................................................................................................................207
CR4C ................................................................................................................................................208
CR4D ................................................................................................................................................209
CR4E.................................................................................................................................................210
CR4F.................................................................................................................................................210
CR50.................................................................................................................................................211
CR51.................................................................................................................................................211
CR52.................................................................................................................................................212
CR53.................................................................................................................................................212
CR54.................................................................................................................................................213
Logical Device Base I/O Address and Range..............................................................................215
Note A. Logical Device IRQ and DMA Operation........................................................................217
Chapter 11
Operational Description...............................................................................................218
11.1
Maximum Guaranteed Ratings....................................................................................................218
11.2
DC Electrical Characteristics .......................................................................................................218
Chapter 12
Timing Diagrams ..........................................................................................................222
12.1
Power-up Timing..........................................................................................................................222
12.2
Input Clock Timing .......................................................................................................................223
12.3
LPC Timing (LPC Mode Only) .....................................................................................................224
12.4
X-Bus Timing (LPC Mode Only)...................................................................................................226
12.4.1
X-Bus I/O Timing...............................................................................................................................226
12.4.1.1
X-Bus I/O Read Timing..................................................................................................................226
12.4.1.2
X-Bus I/O Write Timing..................................................................................................................227
12.4.2
Representative LPC I/O Cycle to X-Bus Cycle Timing......................................................................228
12.4.2.1
X-Bus I/O Read Cycle: LPC I/O Read Cycle – Data from X-Bus Device to Host...........................228
12.4.2.2
X-Bus I/O Write Cycle: LPC I/O Write Cycle - Data from Host to X-Bus Device............................229
12.4.3
X-Bus Memory Cycle Timing.............................................................................................................230
12.4.3.1
Timing For FWH and LPC initiated Memory Read Cycles with the X-Bus.....................................230
12.4.3.2
Timing For FWH and LPC initiated Memory Write Cycles with the X-Bus.....................................231
12.5
Host Timing (ISA Mode Only)......................................................................................................232
12.6
Floppy Disk Timing.......................................................................................................................234
12.7
EPP Parallel Port Timing .............................................................................................................235
12.8
ECP Parallel Port Timing .............................................................................................................238
12.8.1
Parallel Port FIFO (Mode 101)..........................................................................................................238
12.8.2
ECP Parallel Port Timing ..................................................................................................................238
12.8.3
Forward-Idle......................................................................................................................................238
12.8.4
Forward Data Transfer Phase...........................................................................................................238
12.8.5
Reverse-Idle Phase...........................................................................................................................238
12.8.6
Reverse Data Transfer Phase...........................................................................................................238
12.8.7
Output Drivers...................................................................................................................................239
12.9
IR Timing......................................................................................................................................242
12.10
Serial IRQ Timing .....................................................................................................................245
12.11
UART Timing ............................................................................................................................246
Chapter 13
XNOR-Chain Test Mode..............................................................................................247
10.5
10.6